1. Field of the Invention
The present invention relates to a multi-processor system and a message transferring method for a multi-processor system, and more particularly, to a multi-processor system, in which a message is transferred between a plurality of processors.
2. Description of the Related Art
There has been known a multi-processor system provided with a plurality of processors such as micro processing units (MPUs). In the multi-processor system, the plurality of processors may transfer messages to each other. As message transferring methods, there are known a method in which a memory independently managed by each of the processors is directly accessed by other processors; a method in which a shared memory is freely accessed by all of the processors; and a method in which a memory region of a shared memory is divided into a region independently managed by each of the processors and a region freely accessed by all of the processors. Here, a “message” is referred to as a unit of data to be transferred.
A buffer managing method is disclosed in Japanese Laid Open Patent Publication (JP-A-Heisei 6-44191: a first conventional example). This first conventional example is relevant to a buffer managing method for a multi-processor system, in which data is temporarily stored in a buffer region when the data is transferred between a plurality of processors. A plurality of buffer regions are provided to be independently managed by the processors, respectively. Each processor controls a reserving process in case of use of the buffer region and a releasing process in case of no necessity of the buffer region to manage the buffer region.
FIG. 1 is a block diagram showing the configuration of the conventional multi-processor system of the first conventional example. The multi-processor system 101 is provided with a plurality of processors (e.g., MPUs) 102-1 to 102-n and a shared memory 103 connected to the processors 102-1 to 102-n via a bus 104. The shared memory 103 has a plurality of message buffers 108-1 to 108-n respectively corresponding to the plurality of processors 102-1 to 102-n. Each of the plurality of processors 102-1 to 102-n manages a corresponding one of the plurality of message buffers 108-1 to 108-n. For example, the message buffer 108-1 is managed by the processor 102-1.
FIG. 2 is a block diagram illustrating the operation of the first conventional example of multi-processor system shown in FIG. 1. Here, it is assumed that there are provided two processors 102-1 and 102-2, in which a message is transmitted from the processor 102-1 to the processor 102-2. At this time, the multi-processor system 101 operates as follows: (1) the processor 102-1 issues a request for reserving a message storage region to the message buffer 108-1 managed by the processor 102-1 per se, thereby reserving the message storage region in the message buffer 108-1; (2) the processor 102-1 transfers a message to the message storage region; (3) the processor 102-2 reads out the message stored in the message buffer 108-1; (4) the processor 102-2 notifies the processor 102-1 of the release of the message storage region in the message buffer 108-1; and (5) the processor 102-1 releases the message storage region in the message buffer 108-1. In this way, the processor 102 manages the reservation and release of the message storage region in the message buffer 108. As the managing method, a method for managing “free or in use” with a bit map and a chain managing method.
In the above example, only one message buffer 108-1 is used, and an FIFO method is adopted for the message buffer 108-1 as a message managing method. As a consequence, a sequence of messages can be kept, but the priorities of messages cannot be reflected. Therefore, a technique is demanded in which the function and performance of the multi-processor system are fulfilled by giving a priority to a message and increasing options of applications.
Furthermore, in order to avoid any confliction of accesses to management data of the message buffer 108 by the plurality of processors 102, the management data of the message buffer 108-1 is managed only by the assigned processor 102-1. In addition, the reserving process and releasing process of the message storage region in the message buffer 108-1 are independently performed by the processor 102-1. Therefore, after the processor 102-2 as a data transmission destination (i.e., on a reception side) receives the message, the processor 102-2 cannot directly perform the releasing process of the message storage region, thereby producing a slight time difference (i.e., a delay) until the processor 102-1 has performed the releasing process. As a result, a technique has been desired such that such a time difference (i.e., a delay) should be eliminated, so as to enhance the throughput of communications between the processors.